Using Contrapositives to Enhance the Implication Graphs of Logic Circuits

Implication graphs are used to solve the test generation, redundancy identification, synthesis, and verification problems of digital circuits. We propose a new “oring” node structure to represent partial implications in a graph. The oring node is the contrapositive of the previously used “anding” node. The addition of a single oring node in the implication graph of a Boolean gate eliminates the need for several anding nodes. An n-input gate requires one oring and one anding nodes to represent all partial implications. This implication graph is shown to be more complete and more compact compared to the previously published (n+1) anding nodes graph. Introduction of the new oring node finds more redundancies using the transitive closure method. The second contribution of the present work is new algorithms to update transitive closure for every newly added edge in the implication graph associated with anding and oring nodes. For the ISCAS’85 benchmark circuit c1908, the new graph identifies 5 out of a total of 7 redundant faults. The best known previous implication graph procedure could only identify 2 redundant faults. We analyze the unidentified redundant faults and suggest a possible improvement.